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7 articles for “VLSI technology”
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Polynomial Thevenin Resistance Networks for Spice Simulation
Abstract: Two networks with resistors and independent sources are considered to compute Thevenin resistance. A different network is considered where the Thevenin resistance from the previous independent networks is to be incorporated (in a polynomial representation). Different methods using Spice/Pspice software to obtain the above representation are described. SPICE/OrCAD software is used to obtain equivalent circuits for Thevenin equivalent network parameters used in polynomial form are described and other different networks …
Published in International Journal of Microelectronics and Digital integrated circuits · Vol. 10, Issue 2, 2024 · pp. 22–36 Read article
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Design and Implementation of BIST Using VERILOG HDL
Abstract: Very large scale integration has had a significant impact in a very short span of time on the growth of integrated circuit technology. It has reduced the size and, more importantly, the cost, it increases the circuit complexity. However, there are potential issues that may delay the effective use and growth of future VLSI technology. Among these is the issue of circuit testing, which is becoming increasingly difficult as the …
Published in International Journal of Microelectronics and Digital integrated circuits · Vol. 5, Issue 1, 2019 · pp. 1–8 Read article
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Performance Analysis of Effect of Underlap with Fixed Gate Length: GaN-based Double Gate MOSFET
Abstract: The effect of gate length 8 nm with underlap of double gate MOSFET has been designed for VLSI Technology. The evaluation process was followed by NEGF (non-equilibrium Green’s function) formalism using SILVACO ATLAS followed to ITRS–2013. The investigations on the threshold voltage, Sub threshold Slope, ION, IOFF, ION/IOFF, DIBL and switching characteristics of the electric field have been done with the simulation results. In the simulation, adopting symmetrical distances from …
Published in International Journal of Applied Nanotechnology · Vol. 6, Issue 2, 2020 · pp. 19–25 Read article
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Design CMOS Low Power High Speed Digital 4-Bit Counter at 45 GPDK Technology
Abstract: The low power VLSI circuit is meant to reduce power consumption, chip size, and improve the system'sbattery life and performance. The scaling design, often known as a counter, is used to increase ordecrease the values of an operator based on its prior state. Frequency and time may be monitoredthroughout the counting process. The main issue with scaling circuits is power consumption caused bypower dissipation in the clock while it is …
Published in International Journal of Microwave Engineering and Technology · Vol. 9, Issue 1, 2023 · pp. 40–51 Read article
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Comparison of Different Full Adders and its Applications
Abstract: Full Adder is a fundamental block in Arithmetic and Logical unit (ALU) which is a core of any processor. It is extensively used in General Purpose Processors (GPP) along with various Application Specific Processors (ASP) like Digital Signal Processor (DSP) for addition, subtraction, multiplication and counting operations. Reducing the power of most repetitively used block in a circuit reduces the overall power of the circuit. Adopting Low Power techniques ensures …
Published in International Journal of Analog Integrated Circuits · Vol. 9, Issue 1, 2023 · pp. 20–35 Read article
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Integration of Electronic Devices and the current applied MOS Techniques
Abstract: This is a research based review of the comprehensive view of our understandings for VLSI which is evolved from integrated circuits with a numbers of transistors ranging from several billions of devices which also include chip and sensors. The VLSI concept based design and implementation are categorized accordingly. It deals with architectural factors, which also describe these for both general-purpose and digital systems and their coexistence with analog, mixed-signal and …
Published in International Journal of Microelectronics and Digital integrated circuits · Vol. 1, Issue 1, 2015 · pp. 7–15 Read article
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A Review on Performance Analysis of CMOS Inverter
Abstract: In this paper, first we study the various inverter circuits and analyze its performance in terms of noise margin, area, power dissipation and computational delay. After that analyze the various parameter of CMOS Inverter circuit using Pyxis schematic tools of Mentor graphics with TSMC 018 CMOS process technology. Based on this simulation, analyze the rise time, fall time and dynamic power dissipation of CMOS inverter. Finally, we got the good …
Published in International Journal of Computer Aided Manufacturing · Vol. 5, Issue 1, 2019 · pp. 29–35 Read article