1 publication

• Published Subscription 29 Jul 2019

  High-Performance FinFET Based 8T SRAM with Enhanced Performance Parameters Using Self-Controllable Voltage level (SVL) Technique

  By Nikhil Saxena, Vaibhav Shrivastava

  Abstract: The scaling of standard single-gate bulk CMOS faces great challenge in the nanometer regime due to the severe short-channel effects (SCE) which causes significant increase in the leakage current. In this paper, a high-performance eight transistor (8T) SRAM has been proposed for reduction in leakage current and power consumption using double-gate FinFET with the proposed technique. Double gate FinFET has better SCEs performance compared to conventional CMOS. In this paper, …

  Published in International Journal of Microelectronics and Digital integrated circuits · Vol. 5, Issue 1, 2019 · pp. 16–24 Read article →