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Comparative Analysis of Multi- Synchronous Bidirectional Network-on-Chip ArchitectureBy Bharati Sayankar, Pankaj Rangaree
Abstract: ABSTRACTA dynamic reconfigurable multi-synchronous bidirectional channel network on chip architecture is proposed to improve the performance of on chip communication. This work aims to increase network-on-chip (NOC) in the runtime traffic situation. The main objective of this paper is to reduce the area, delay and power consumption of the architecture. Lower packet delivery latency, higher packet consumption rate and better bandwidth utilization is done by the multi-synchronous bidirectional NoC’s router. …
Published in International Journal of Telecommunications & Emerging Technologies · Vol. 5, Issue 2, 2019 · pp. 21–31 Read article →