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Low Power, High Reliability: A Survey of 10T SRAM Cells for Reduced Stand by Power and Enhanced Noise ResilienceBy K. Joseph Thanusha, Anusha Achhina, Deepya Yennamaneni
Abstract: With a focus on maximising power efficiency and attaining good read stability and write-ability, the project presents a low standby power 10T (LP10T) SRAM cell. The Schmitt-trigger inverter and the double-length pull-up transistor are combined with a regular inverter and stacked transistor to form a robust cross-coupled structure used in the LP10T SRAM cell. One of the key advantages of the LP10T SRAM cell is that it separates the read …
Published in International Journal of Microelectronics and Digital integrated circuits · Vol. 9, Issue 1, 2023 · pp. 34–56 Read article →